The subject matter disclosed herein relates to integrated circuit devices. More particularly, the subject matter relates to monitoring structures in integrated circuit (IC) devices.
Low-k dielectrics, in particular porous low-k materials, are introduced in the back-end-of-line (BEOL) portion of an IC device to lower the k-value (the dielectric constant) and thereby minimize time delay in the interconnection of the circuitry. Sub-32 nm technology calls for ultra-low-k porous dielectric materials (e.g., k<2.5) for copper interconnects in the BEOL to reduce resistance-capacitor (RC) delay. However, although the k-value decreases with increasing porosity (as required to minimize RC delay), the mechanical strength of these materials is also reduced, making them susceptible to structural damage (e.g., cracks, delamination). Due to a mismatch in the coefficient of thermal expansion (CTE) of different materials, the packaging process can cause large shear forces to act on the chip at the BEOL portion, in particular, at the corners of the chip. These shear forces may lead to cracks in the BEOL portion. In addition, packaging technology such as micro-bumps, copper pillars, and through-silicon vias (TSVs) can introduce local stress in the BEOL portion. This local stress can also lead to damage of the weak low-k material underneath the BEOL. These problems are typically described as Chip Package Interaction (CPI). With thinning and stacking of chips for expanding three-dimensional (3D) technology, these problems can become even more acute. As such, in advanced technologies, additional mechanical forces can quickly lead to failure of the BEOL layers.
Monitoring and testing for CPI, particularly in the BEOL can be challenging. In particular, chip-to-chip variation and design-to-design variation have made conventional testing approaches ineffective at consistently identifying CPI in advanced technology ICs.